1. Field of the Invention
The present invention relates to programmable metallization cell (PMC) technology.
2. Description of Related Art
Programmable Metallization Cell (PMC) technology is being investigated for use in nonvolatile memory, reconfigurable logic, and other switching applications due to its low current, good scalability, and high programming speed. The resistance switching of PMC devices is manifested by growing and removing conducting bridges through an electrochemical or electrolytic process. Therefore, PMC devices have also been referred to as conducting bridge (CB) devices or electrochemical (EC) devices.
PMC devices have an ON state in which the conductive bridge completes a current path between electrodes, and an OFF state in which the conductive bridge is reduced such that it does not complete a current path between the electrodes. When arranged in a memory array, underlying transistors, diodes and other access devices are required to prevent current flow from unselected cells in the ON state from interfering with read operations, and other operations on selected cells.
Many three-dimensional (3D) memory concepts have been proposed in order to make high density memory. Li et al., “Evaluation of SiO2 Antifuse in a 3D-0TP Memory,” IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 4, NO. 3, Sep. 2004, describes a polysilicon diode and an anti-fuse arranged as a memory cell. Sasago et al., “Cross-point phase change memory with 4F2 cell size driven by low-contact-resistivity poly-Si diode,” 2009 Symposium on VLSI Technology Digest of Technical Papers, pages 24-25, describes a polysilicon diode and a phase change element arranged as a memory cell. Kau et al., “A stackable cross point phase change memory,” IEDM09-617, (2009) pages 27.1.1 to 27.1.4, describes a memory cell including an ovonic threshold switch 0TS as an isolation device with a phase change element. These technologies rely on a combination of an isolation device and a memory element to construct the memory cell. The isolation device adds extra processes and thickness and/or area to the memory structure. Also, the isolation device/memory element approach is not suitable for many 3D memory structures, including so called Bit Cost Scalable BiCS structures and other 3D memory structures that include a large number of memory layers.
In Chen et al., “An Access-Transistor-Free (0T/1R) Non-Volatile Resistance Random Access Memory (RRAM) Using a Novel Threshold Switching, Self-Rectifying Chalcogenide Device,” IEDM 03-905, (2003), pages 37.4.1 to 37.4.4, a so-called zero transistor/one resistor 0T/1R memory cell is described using a phase change element that does not include a separate isolation device. (See, also, U.S. Pat. No. 7,236,394).
Therefore, it is desirable to provide a memory technology that is suitable for high density structures such as in so-called 0T/1R arrays, and is easily manufactured.